I. Field of the Invention
This invention relates to a method of fabricating a Schottky gate field effect transistor (FET), and more particularly, to a method of fabricating a Schottky gate field effect transistor based on a III-V Group compound semiconductor.
II. Description of the Prior Art
Among the III-V Group compound semiconductors, a Schottky gate field effect transistor (also referred to as a "metal semiconductor (MES)FET") based on gallium arsenide (GaAs) has an excellent high frequency property and is widely accepted as a discrete semiconductor element constituting a high frequency amplifier or oscillator. Recently, this GaAs MESFET has played an important role as a basic element of a gallium arsenide integrated circuit (GaAs IC).
As is well known in the art, the figure of merit of MESFETs in high frequency bands is expressed as Cgs/gm (where Cgs denotes the capacitance between the gate and source, and gm represents mutual conductance). It can be understood that the figure of merit can be improved by reducing the gate-source capacitance and/or enlarging the mutual conductance. The mutual conductance gm is expressed by the following formula: EQU gm=gm.sub.0 /(1+gm.sub.0 Rs) (A)
where:
gm.sub.0 =intrinsic mutual conductance determined from the property of the channel section of the MESFET PA1 Rs=series resistance between the source and gate.
It is seen that in practice, the mutual conductance gm is reduced to a smaller value than a maximum value gm.sub.0 due to the presence of the parasitic resistance Rs. For enlargement of the mutual conductance gm, therefore, it is necessary to reduce Rs, and consequently, to reduce the distance between the source and gate. Alternatively, the enlargement of the mutual conductance gm can also be effected by increasing gm.sub.0.
It is known that the source-gate capacitance Cgs is proportional to a gate length Lg, and the intrinsic mutual conductance gm.sub.0 is inversely proportional to the gate length Lg. Therefore, the shortening of the gate length Lg can reduce the source-gate capacitance Cgs and enlarge the mutual conductance gm.
In order to improve the high frequency property of the MESFET, therefore, it is necessary to develop a technique to reduce parasitic resistance and/or to shorten the gate length.
Self-alignment methods have attracted attention as useful means for reducing parasitic resistance. A typical process of this type is, for example, the type which utilizes the overhang of a photoresist as set forth in, for example, Electronics Letters, December 1981, pp. 944-945. Description will now be given with reference to FIGS. 1A to 1C of the fundamental steps of the process. Referring to FIG. 1A, a metal layer 13 used as a gate electrode is deposited on the surface of an active layer 12 formed on a GaAs substrate 11. A patterned photoresist 14 having a width L is formed on the metal layer 13. This metal layer 13 is selectively removed by isotropic etching with the photoresist 14 used as a mask. As a result, overhanging portions 14a, 14b corresponding to the extent (.DELTA.x) of the lateral etching of the metal layer 13 are formed in the photoresist 14 (FIG. 1B). The remaining portion 13a of the metal layer 13 is the gate electrode. An ohmic-contacting metal layer is deposited on the structure shown in FIG. 1B. This ohmic-contacting metal layer is divided by the photoresist 14 into two portions 15a, 15b on the active layer 12. A separate portion 15c of the ohmic-contacting metal layer is formed on the photoresist 14 (FIG. 1C). Finally, the photoresist 14, together with the overlying separate metal layer 15c, is removed to finish the MESFET.
According to the above-mentioned process, the distance between the source and gate electrodes and the distance between the gate and drain electrodes are defined by a relatively small extent (.DELTA.x) of lateral etching. Therefore, the source and drain electrodes can be set close to the gate electrode, thereby reducing parasitic resistance. Further, the above-mentioned process has the advantage that the gate length can be shortened to that which is arrived at by subtracting twice the extent (.DELTA.x) of the lateral etching from the width L of the photoresist 14. In other words, the aforementioned process indeed has the merit of satisfying the two previously described requirements, but this process has the drawback that difficulties are presented in rigidly controlling the extent (.DELTA.x) to which the thin metal layer used as a gate electrode is isotropically etched laterally, resulting in a decline in reproducibility. Particularly with respect to GaAs LSI, the conventional process presents considerable difficulties in satisfying the requirements of fixing the gate lengths over the whole surface of a wafer.